SCR5 efficient application core (RV32 or RV64)

Efficient 32- or 64bit Linux-capable application core with virtual memory, MMU, L1/L2 caches, coherency and SMP support

Block diagram

Key features

  • Efficient entry-level 32- or 64bit RISC-V application core
  • Harvard architecture, separate Instruction and Data memories
  • Multicore configs support up to 4 SCRx cores
    • SMP and heterogeneous
  • 7 to 9 stages pipeline, 1GHz+ @tsmc28
  • User-, Supervisor- and Machine-mode privilege levels
  • Fully-featured memory subsystem with Linux support
    • Memory Managements Unit (MMU)
    • Page-based virtual memory
    • L1 and L2 caches with coherency, HW atomics, ECC
  • High-performance IEEE 754-2008 compliant floating-point unit
    • Configurable single or double precision FP unit
    • 32 floating-point data registers
  • AXI4- or AHB- compliant external interface
  • Configurable Integrated Programmable Interrupt Controller (IPIC) and PLIC
    • up to 1024 IRQs
    • Low interrupt latency
  • Advanced Integrated Debug Controller
    • JTAG compliant interface
    • HW/SW breakpoints support
    • ROM breakpoints support

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