RISC-V is a free, open, universal and extensible instruction set architecture (ISA), targeted at the wide range of the applications. RISC-V Foundation, a non-profit industry consortium drives development and promotion of the ISA with a primary goal to establish RISC-V as a standard universal processor architecture for all applications, from MCU to HPC. Syntacore is a founding member of the Foundation and one of the first commercial IP vendors already sampling RISC-V based client SoCs. For more details and complete ISA specifications, visit www.riscv.org.

Voted as The Best Technology of 2016 by Analysts’ Choice Awards, The Linley Group:

“RISC-V is a general-purpose instruction set architecture that is extensible and royalty free. It’s clean and modular with a 32-, 64-, or 128-bit integer base and various optional extensions. RISC-V is flexible enough to serve all markets, from MCUs to server processors. Implementations vary, from FPGAs to synthesized macros to fully custom layouts. It’s extensible, so designers can customize it for special-purpose workloads.”

The Linley Group Microprocessor Report, 2017