SCR3 Microcontroller Core (RV32 or RV64)

High-performance 32 or 64bit multicore capable MCU-class core with privilege modes and MPU

Block diagram

Key features

  • Harvard architecture, separate Instruction and Data memories
  • RV32I[MCA] or RV64I[MCA] ISA
  • 32 integer registers
  • AXI4- or AHB-compliant external interface (configurable option)
  • Configurable 3 to 5 stages pipeline implementation
  • User- and Machine-mode privilege levels
  • Optional Memory Protection Unit (MPU)
  • Tightly Coupled Memory (TCM) support, L1 caches ECC/parity
  • Optional configurable Integrated Programmable Interrupt Controller (IPIC) and PLIC
    • up to 1024 IRQs
    • Low interrupt latency
  • Optional high-performance or area-optimized MUL/DIV unit
  • Advanced Integrated Debug Controller
    • JTAG-compliant interface
    • HW/SW breakpoints support
    • ROM breakpoints support
  • Multicore configs up to 4 SCRx cores
    • SMP and heterogeneous
    • with memory coherency

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